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La description: CADENCE LIRARIES/INTRFC MAINT
La description: INTEGRAPH SCHEM SYNTH/SIM LIBRA
La description: EXEMPLAR SYNTHESIS LIBS/INTRFC
La description: SYNOPSYS LIBRARIES/INTRFC MAINT
La description: INTEGRAPH SCHEM SYNTH/SIM MAINT
La description: SOFTWARE DESIGN PROCHIP
La description: MAINT EXEMPLAR SYNTHESIS
La description: PRO CHIP SOFTWARE LICENSE
La description: SYNOPSYS LIBRARIES/INTRFC MAINT
La description: MENTOR V8 LIBRARIES/INTRFC MAINT
La description: CADENCE VERILOG LIB/INTRFC MAINT
La description: EXEMPLAR SYNTHESIS LIBS/INTRFC
La description: FPGA DESIGN SYS W/VWDRAW/VIEWSIM
La description: ATMEL SYNARIO VERILOG SIM OPTION
La description: ATMEL SYNARIO VHDL SYNTHESIS OPT
La description: ATMEL SYNARIO VHDL SYNTHESIS OPT
La description: ATMEL SYNARIO BASIC PACKAGE
La description: MENTOR V8 LIBRARIES/INTERFACE
La description: UNIV AT6000 PHYSICAL DESIGN SYS
La description: FPGA DESIGN SYSTEM W/VIEWDRAW
2025/05/20